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Chisel/Rocket-chip/RISC-V线下交流会

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活动详情

你或许已经对RISC-V有所了解，但你或许会更加好奇RISC-V的发明者和SiFive这家公司到底是怎样工作的？


你或许听朋友们说起Chisel这门新的硬件构建语言，但却对他存在很多困惑和不解。你需要一个平台为你答疑解惑，同样你也需要一个平台与业界的朋友们一起聊聊RISC-V和Chisel那些事儿。


本年度的图灵奖演讲上：David Patterson和John Hennessy提出我们要迎接计算机体系结构的黄金时代，而敏捷硬件开发和像RISC-V这样的开放架构也在其中。


9月8日下午，在张江Vπ空间，SiFive的开发团队和国内的chisel爱好者们将分享他们在RISC-V、Chisel、FireSim、Firrtl、TileLink、diplomacy等方面的经验和想法。


这是一次聚会、也是一次聆听；是一次共享、更是一次思维的碰撞。精彩的让你不容错过。快来加入我们吧！


（感谢 矽说 提供自媒体宣传支持）


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活动日程
2018-09-08
13:30-14:00

签到

14:00-15:00

Building RISC-V SoCs with Chisel, FIRRTL, Rocket-Chip, Diplomacy, and TileLink

嘉宾
Chisel/Rocket-chip/RISC-V线下交流会
Krste Asanovic
Professor at UC Berkeley, Co-Founder & Chief Architect at SiFive
Chisel/Rocket-chip/RISC-V线下交流会
Yunsup Lee
Co-Founder & Chief Technology Officer, SiFive
15:00-15:20

Implement a simple L2 Network Switch in Chisel

嘉宾
Chisel/Rocket-chip/RISC-V线下交流会
Alex Guo
Embedded System Design Director, JL Semi
15:20-15:40

Extending Rocket Chip with Verilog Peripheral IPs


嘉宾
Chisel/Rocket-chip/RISC-V线下交流会
Wei Song
Associate Professor, Institute of Information Engineering, CAS
15:40-16:00

The cases of Chisel in education and research projects

嘉宾
Chisel/Rocket-chip/RISC-V线下交流会
Zihao Yu
PhD Candidate, Institute of Computing Technology, Chinese Academy of Sciences
16:00-17:30

Lightning Talk & Discussion

签到

Building RISC-V SoCs with Chisel, FIRRTL, Rocket-Chip, Diplomacy, and TileLink

Chisel/Rocket-chip/RISC-V线下交流会
Krste Asanovic
Professor at UC Berkeley, Co-Founder & Chief Architect at SiFive
Krste is SiFive’s Chief Architect and a co-founder. Krste is also a Professor in the EECS Department at the University of California, Berkeley, where he is Director of the ASPIRE Lab. Krste leads the RISC‑V ISA project at Berkeley, and is Chairman of the RISC-V Foundation. He is an ACM Distinguished Scientist and an IEEE Fellow. Krste received his PhD from UC Berkeley, and a BA in Electrical and Information Sciences from the University of Cambridge.
Chisel/Rocket-chip/RISC-V线下交流会
Yunsup Lee
Co-Founder & Chief Technology Officer, SiFive
Yunsup is SiFive’s Chief Technology Officer and co-founder. Yunsup received his PhD from UC Berkeley, where he co-designed the RISC-V ISA and the first RISC-V microprocessors with Andrew Waterman, and led the development of the Hwacha decoupled vector-fetch extension. Yunsup also holds an MS in Computer Science from UC Berkeley and a BS in Computer Science and Electrical Engineering from the Korea Advanced Institute of Science and Technology (KAIST).

Implement a simple L2 Network Switch in Chisel

Chisel/Rocket-chip/RISC-V线下交流会
Alex Guo
Embedded System Design Director, JL Semi
Alex Guo is the Embedded System Design Director at Jinglue Semiconductor (Shanghai) and an Individual Member in RISC-V Foundation. He has 8 years R&D experience in digital IC design and software development. An open source fan and a contributor.

Extending Rocket Chip with Verilog Peripheral IPs


Chisel/Rocket-chip/RISC-V线下交流会
Wei Song
Associate Professor, Institute of Information Engineering, CAS
Wei Song is an Associate Professor at the Institute of Information Engineering, CAS. He holds a PhD from the University of Manchester. During 2014 to 2017, Wei worked for the lowRISC project at the University of Cambridge. He led the first four versions of the lowRISC SoC, which extended the Rocket chip with extra features including tagged memory, trace debugger and minion cores.

The cases of Chisel in education and research projects

Chisel/Rocket-chip/RISC-V线下交流会
Zihao Yu
PhD Candidate, Institute of Computing Technology, Chinese Academy of Sciences
Zihao Yu is a PhD candidate of Institute of Computing Technology, Chinese Academy of Sciences. He is supervised by Prof. Ninghui Sun and Prof. Yungang Bao. He received his B.S. degree in computer science from Nanjing University in 2014. His research interests include computer architecture and operating systems. He is the leader of the Labeled RISC-V project.

Lightning Talk & Discussion

活动嘉宾
PhD Candidate, Institute of Computing Technology, Chinese Academy of SciencesZihao Yu
Zihao Yu
PhD Candidate, Institute of Computing Technology, Chinese Academy of Sciences
Zihao Yu is a PhD candidate of Institute of Computing Technology, Chinese Academy of Sciences. He is supervised by Prof. Ninghui Sun and Prof. Yungang Bao. He received his B.S. degree in computer science from Nanjing University in 2014. His research interests include computer architecture and operating systems. He is the leader of the Labeled RISC-V project.
Associate Professor, Institute of Information Engineering, CASWei Song
Wei Song
Associate Professor, Institute of Information Engineering, CAS
Wei Song is an Associate Professor at the Institute of Information Engineering, CAS. He holds a PhD from the University of Manchester. During 2014 to 2017, Wei worked for the lowRISC project at the University of Cambridge. He led the first four versions of the lowRISC SoC, which extended the Rocket chip with extra features including tagged memory, trace debugger and minion cores.
Embedded System Design Director, JL SemiAlex Guo
Alex Guo
Embedded System Design Director, JL Semi
Alex Guo is the Embedded System Design Director at Jinglue Semiconductor (Shanghai) and an Individual Member in RISC-V Foundation. He has 8 years R&D experience in digital IC design and software development. An open source fan and a contributor.
Co-Founder & Chief Technology Officer, SiFiveYunsup Lee
Yunsup Lee
Co-Founder & Chief Technology Officer, SiFive
Yunsup is SiFive’s Chief Technology Officer and co-founder. Yunsup received his PhD from UC Berkeley, where he co-designed the RISC-V ISA and the first RISC-V microprocessors with Andrew Waterman, and led the development of the Hwacha decoupled vector-fetch extension. Yunsup also holds an MS in Computer Science from UC Berkeley and a BS in Computer Science and Electrical Engineering from the Korea Advanced Institute of Science and Technology (KAIST).
Professor at UC Berkeley, Co-Founder & Chief Architect at SiFiveKrste Asanovic
Krste Asanovic
Professor at UC Berkeley, Co-Founder & Chief Architect at SiFive
Krste is SiFive’s Chief Architect and a co-founder. Krste is also a Professor in the EECS Department at the University of California, Berkeley, where he is Director of the ASPIRE Lab. Krste leads the RISC‑V ISA project at Berkeley, and is Chairman of the RISC-V Foundation. He is an ACM Distinguished Scientist and an IEEE Fellow. Krste received his PhD from UC Berkeley, and a BA in Electrical and Information Sciences from the University of Cambridge.
Zihao Yu
Chisel/Rocket-chip/RISC-V线下交流会
PhD Candidate, Institute of Computing Technology, Chinese Academy of Sciences
Zihao Yu is a PhD candidate of Institute of Computing Technology, Chinese Academy of Sciences. He is supervised by Prof. Ninghui Sun and Prof. Yungang Bao. He received his B.S. degree in computer science from Nanjing University in 2014. His research interests include computer architecture and operating systems. He is the leader of the Labeled RISC-V project.

The cases of Chisel in education and research projects

18年09月08日 15:40 --16:00
Wei Song
Chisel/Rocket-chip/RISC-V线下交流会
Associate Professor, Institute of Information Engineering, CAS
Wei Song is an Associate Professor at the Institute of Information Engineering, CAS. He holds a PhD from the University of Manchester. During 2014 to 2017, Wei worked for the lowRISC project at the University of Cambridge. He led the first four versions of the lowRISC SoC, which extended the Rocket chip with extra features including tagged memory, trace debugger and minion cores.

Extending Rocket Chip with Verilog Peripheral IPs


18年09月08日 15:20 --15:40
Alex Guo
Chisel/Rocket-chip/RISC-V线下交流会
Embedded System Design Director, JL Semi
Alex Guo is the Embedded System Design Director at Jinglue Semiconductor (Shanghai) and an Individual Member in RISC-V Foundation. He has 8 years R&D experience in digital IC design and software development. An open source fan and a contributor.

Implement a simple L2 Network Switch in Chisel

18年09月08日 15:00 --15:20
Yunsup Lee
Chisel/Rocket-chip/RISC-V线下交流会
Co-Founder & Chief Technology Officer, SiFive
Yunsup is SiFive’s Chief Technology Officer and co-founder. Yunsup received his PhD from UC Berkeley, where he co-designed the RISC-V ISA and the first RISC-V microprocessors with Andrew Waterman, and led the development of the Hwacha decoupled vector-fetch extension. Yunsup also holds an MS in Computer Science from UC Berkeley and a BS in Computer Science and Electrical Engineering from the Korea Advanced Institute of Science and Technology (KAIST).

Building RISC-V SoCs with Chisel, FIRRTL, Rocket-Chip, Diplomacy, and TileLink

18年09月08日 14:00 --15:00
Krste Asanovic
Chisel/Rocket-chip/RISC-V线下交流会
Professor at UC Berkeley, Co-Founder & Chief Architect at SiFive
Krste is SiFive’s Chief Architect and a co-founder. Krste is also a Professor in the EECS Department at the University of California, Berkeley, where he is Director of the ASPIRE Lab. Krste leads the RISC‑V ISA project at Berkeley, and is Chairman of the RISC-V Foundation. He is an ACM Distinguished Scientist and an IEEE Fellow. Krste received his PhD from UC Berkeley, and a BA in Electrical and Information Sciences from the University of Cambridge.

Building RISC-V SoCs with Chisel, FIRRTL, Rocket-Chip, Diplomacy, and TileLink

18年09月08日 14:00 --15:00
活动主办方
时间与地址
时间: 2018-09-08 13:30 ~ 17:30
地址:   上海浦东新区碧波路635号传奇广场一楼Vπ空间
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