茶歇&合影&展区参观 Tea Break & Group Photo & Exhibition Tour
2026-09-16
10:50-14:00
架构演进：下一代E/E架构与芯片选型Architecture Evolution: Next‑Gen E/E Architecture and Chip Selection
舱驾融合、端侧大模型、物理AI落地，车企如何选芯片？国产芯片如何"上车"？直击真实量产痛点Integration of cockpit and ADAS, on‑device large models, physical AI deployment – how should OEMs choose chips? How can domestic chips get into vehicles? Tackling real‑world mass‑production pain points.
2026-09-16
10:50-11:10
舱驾融合：一颗芯片如何统管整车"数字大脑"
Cockpit‑ADAS Integration: How a Single Chip Manages the Vehicle’s "Digital Brain"
热点对话：芯片“上车”的最后一公里：准入机制、选型博弈与量产实战
Panel：The Last Mile for Chips to "Get on Board" – Qualification Mechanisms, Selection Strategies & Mass‑Production Practices
午餐&VIP午宴&展区参观 Lunch, VIP Luncheon, and Exhibition Tour
2026-09-16
14:00-16:10
底层攻坚：产业链协同（制造·封装·测试）Core Breakthrough: Industry Chain Synergy (Manufacturing · Packaging · Testing)
从功率半导体到RISC-V，从成熟制程到先进封装，从晶圆制造到测试良率——打通芯片"能造出来"的全链条From power semiconductors to RISC‑V, from mature nodes to advanced packaging, from wafer fab to test yield – unlocking the full chain of “making chips possible.”
2026-09-16
14:00-14:20
SiC / GaN双轨进化：800V平台与AI电源的功率交汇
SiC/GaN Dual‑Track Evolution: Power Convergence of 800V Platforms and AI Power Supplies
车规芯片测试：测试覆盖率·成本·量产良率
Automotive Chip Testing: Coverage, Cost & Production Yield
华峰测控/长川科技/中科飞测/ 精测电子/苏州芯检
Huafeng Test & Control / Changchuan Tech / Zhongkefeice / Jingce Electronics / Suzhou Xinjian
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2026-09-16
15:40-16:10
茶歇&合影&展区参观 Tea Break & Exhibition Tour
2026-09-16
16:10-18:10
生态共赢：EDA/IP/设备与全球化 Ecosystem Win‑Win: EDA / IP / Equipment & Globalization
从EDA设计到车规IP，从国产工具链上车到芯片出海——构建韧性、开放、协同的产业新生态From EDA design to automotive‑grade IP, from domestic toolchains to chip going global – building a resilient, open, and collaborative new industrial ecosystem.
2026-09-16
16:10-16:30
面向车规芯片的EDA设计·仿真·验证·DFT
EDA Design, Simulation, Verification & DFT for Automotive Chips
车规IP生态：接口IP·安全IP·存储IP·功能安全IP
Automotive‑Grade IP Ecosystem: Interface IP, Security IP, Memory IP, Functional Safety IP
芯原股份/ARM/Imagination/芯动联科
VeriSilicon / ARM / Imagination / Xindonglinke
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2026-09-16
16:50-17:10
从设计到量产：EDA/IP、晶圆制造、封测与测试装备的全链协同与车规准入门槛
From Design to Mass Production: Full‑Chain Synergy of EDA/IP, Wafer Fab, Packaging/Testing & Test Equipment, plus Automotive‑Grade Access Barriers
车规芯片出海：从成本替代到体系输出 + 同源共链赋能新终端
Automotive Chip Going Global: From Cost Substitution to System Export + “Shared‑Chain” Empowerment for New Terminals
地平线
Horizon Robotics
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2026-09-16
17:30-18:10
AI定义汽车时代的"芯"坐标——下一个十年
The "Chip" Coordinates in the AI‑Defined Automotive Era – The Next Decade
一汽/上汽/奇瑞
FAW / SAIC / Chery
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2026-09-16
18:10-18:10
生态共赢：EDA/IP/设备与全球化 Ecosystem Win‑Win: EDA / IP / Equipment & Globalization
从EDA设计到车规IP，从国产工具链上车到芯片出海——构建韧性、开放、协同的产业新生态From EDA design to automotive‑grade IP, from domestic toolchains to chip going global – building a resilient, open, and collaborative new industrial ecosystem.
2026-09-16
18:10-18:10
会议结束 Conference Concludes
汽车芯片竞争新格局：争夺智能汽车控制权
New Landscape of Automotive Chip Competition: The Battle for Smart Vehicle Control
2026车规级芯片产业报告
2026 Automotive‑Grade Chip Industry Report
AI"抢芯"冲击波：存储暴涨如何重塑汽车供应链格局
AI "Chip Grab" Shockwave: How Storage Surge Reshapes the Automotive Supply Chain
车企造芯大爆发：从"买芯"到"造芯"的产业权力转移
OEM Chip Surge: Power Shift from "Buying" to "Making" Chips
智驾芯片"后算力时代"：从TOPS内卷到端到端与世界模型
Post‑TOPS Era for ADAS Chips: From TOPS War to End‑to‑End and World Models
茶歇&合影&展区参观 Tea Break & Group Photo & Exhibition Tour
舱驾融合：一颗芯片如何统管整车"数字大脑"
Cockpit‑ADAS Integration: How a Single Chip Manages the Vehicle’s "Digital Brain"
端侧大模型与物理 AI：为汽车注入 "原生智能"
On‑Device Large Models & Physical AI: Infusing Vehicles with "Native Intelligence"
下一代E/E架构芯片选型：智驾·座舱·电驱·区域控制器的逻辑
Next‑Gen E/E Architecture Chip Selection: Logic for ADAS, Cockpit, E‑Drive & Zone Controllers
热点对话：芯片“上车”的最后一公里：准入机制、选型博弈与量产实战
Panel：The Last Mile for Chips to "Get on Board" – Qualification Mechanisms, Selection Strategies & Mass‑Production Practices
午餐&VIP午宴&展区参观 Lunch, VIP Luncheon, and Exhibition Tour
SiC / GaN双轨进化：800V平台与AI电源的功率交汇
SiC/GaN Dual‑Track Evolution: Power Convergence of 800V Platforms and AI Power Supplies
RISC-V车规元年：开放架构如何构建自主生态
The Year of RISC‑V Automotive‑Grade: How Open Architecture Builds a Self‑Controlled Ecosystem
Chiplet·先进封装·功率封装·异构集成
Chiplet, Advanced Packaging, Power Packaging & Heterogeneous Integration
车规芯片测试：测试覆盖率·成本·量产良率
Automotive Chip Testing: Coverage, Cost & Production Yield
茶歇&合影&展区参观 Tea Break & Exhibition Tour
面向车规芯片的EDA设计·仿真·验证·DFT
EDA Design, Simulation, Verification & DFT for Automotive Chips
车规IP生态：接口IP·安全IP·存储IP·功能安全IP
Automotive‑Grade IP Ecosystem: Interface IP, Security IP, Memory IP, Functional Safety IP
从设计到量产：EDA/IP、晶圆制造、封测与测试装备的全链协同与车规准入门槛
From Design to Mass Production: Full‑Chain Synergy of EDA/IP, Wafer Fab, Packaging/Testing & Test Equipment, plus Automotive‑Grade Access Barriers
HBM与高带宽车载存储：从"卡脖子"到自主突破
HBM & High‑Bandwidth Automotive Memory: From "Bottleneck" to Self‑Breakthrough
车规芯片出海：从成本替代到体系输出 + 同源共链赋能新终端
Automotive Chip Going Global: From Cost Substitution to System Export + “Shared‑Chain” Empowerment for New Terminals
AI定义汽车时代的"芯"坐标——下一个十年
The "Chip" Coordinates in the AI‑Defined Automotive Era – The Next Decade
